1. Field of the Invention
This invention is directed to complementary bipolar transistors, and more particularly, to complementary vertical bipolar NPN and PNP transistors having one symmetrical doping profile for the intrinsic region of both transistors.
2. Description of the Prior Art
The fabrication of complementary bipolar transistors on a common substrate has continued to be plaqued by two major problems. The first problem results from unequal performance characteristics for the NPN and PNP devices. PNP transistor characteristics are inherently inferior to those of NPN transistors as typified by device speed which is lower for an PNP by a factor of 2-20. As a result, it would be necessary to degrade the performance of the NPN transistor to match the performance of the PNP transistor. A second problem arises in the fabrication of the complementary transistors which typically requires numerous, highly precise fabrication steps. The complicated fabrication process increases costs and reduces device reliability.
One prior art example of a complementary transistor structure and method for manufacture that attempts to solve some of the prior art problems can be found in U.S. Pat. No. 4,357,622 to Magdo et al. assigned to the same assignee as the present invention. In the Magdo et al. patent, the NPN and PNP transistors are independently fabricated and optimized. In particular, the doping profiles for the emitter, base and collector regions of each transistor are separately formed. A significant feature of the Magdo et al. patent is the formation of the P-type emitter for the PNP transistor by forming a polycrystalline silicon layer on the exposed surface of the base prior to the last drive-in treatment. After drive-in, doping ions in the polycrystalline layer are driven into the epitaxial layer forming the base to provide a shallow emitter region. The use of this double silicon process has been found to improve the performance of the PNP transistor thereby partially reducing the difference in device characteristics with the NPN transistor.
The use of the Magdo et al. process, while improving performance still results in unequal NPN and PNP devices. For high performance complementary circuit design, both the PNP and the NPN must be of comparable high performance. The key aspects for developing such a structure include a low sub-collector resistance for both the NPN and PNP type devices; high performance NPN and PNP profiles, including narrow base, as well as a steep emitter profile; planarity of the surface of the device for better wirability; and a limitation in the number of masking steps.